1. Field of the Invention
The invention relates to the field of semiconductor memory devices employing floating gates and the processes and methods for fabricating these devices.
2. Prior Art
One class of non-volatile semiconductor memories employs floating gates, that is, gates which are completely surrounded by an insulative layer such as silicon dioxide. Typically, a polycrystalline silicon (polysilicon) layer is used to form floating gates. These gates are electrically charged, most often with electrons by transferring charge into and from the gates through a variety of mechanisms. The presence or absence of this charge represents stored, binary information. An early example of such a device is shown in U.S. Pat. No. 3,500,142.
The earliest commercial electrically programmable read-only memories (EPROMs) employing floating gates used p-channel devices which are programmed through avalanche injection. Charge is removed from these devices by exposing the array to electromagnetic radiation such as ultraviolet light (see U.S. Pat. No. 3,660,819). Later, EPROMs used n-channel devices and relied on channel injection as the mechanism for transferring charge into the floating gates (see U.S. Pat. No. 3,984,822). Many EPROMs fabricated with current technology still rely on channel injection for transferring charge into the floating gates and radiation for erasing the gates.
Another category of semiconductor floating gate memory devices are both electrically programmable and electrically erasable. Such a device is shown in U.S. Pat. No. 4,203,158. Tunneling through a thin oxide region transfers charge into and from the floating gates. In these memories, two devices are required for each memory cell. One device includes the floating gate and the other (typically an ordinary field-effect transistor) is used to isolate the floating gate device during various memory cycles.
A more recent category of floating gate memory devices uses channel injection for charging floating gates and tunneling for removing charge from the gates. Here, each memory cell comprises only a single device and the entire memory array is erased at one time, that is, individual cells or groups of cells are not separately erasable as in current EEPROMs. These memories are sometimes referred to as "flash" EPROMs or EEPROMs.
In some cases, the floating gate memory devices are fabricated in arrays where each device or device pair is separated from other devices by field oxide regions. An example of this is shown in U.S. Pat. No. 4,114,255. In these arrays, a metal contact is needed for each device or device pair. These metal contacts take up substantial substrate area and therefore limit the reduction of device area. Another problem associated with fabricating cells of the type described in the above-mentioned patent is undesirable rounding of the edges of the common source. This rounding increases the floating gate to source tunneling area and therefore the floating gate to source capacitance. Increased tunnel area capacitance degrades the tunnel erase process. Additionally, there is always some misalignment of the polysilicon word line relative to the common source region. Since one dimension of the floating gate is defined in alignment with the word line, the total floating gate to source tunneling area will vary because of the word line misalignment. And, in fact, for each cell pair, due to the mirrored nature of the array, asymmetry will exist between the floating gate-to-source tunneling area for each pair. This causes a bi-modal distribution of the erase threshold. Obviously, it is undesirable to have a wide erase threshold distribution.
U.S. Pat. No. 4,780,424 provides a process for fabricating a buried bit line device which avoids the increased capacitance of the prior art cells. This process includes fabricating contactless electrically programmable and electrically erasable memory cells. Elongated source and drain regions are formed, and then field oxide is grown on top of the source and drain regions. The drain regions are shallow compared to the source regions. Furthermore, the source regions have more graded junctions. The floating gates are formed over a tunnel oxide between the source and drain regions with word lines being disposed perpendicular to the source and drain regions. One dimension of the floating gate is formed simultaneously and in alignment with the word lines.
The programming and erasing function of the memory cells occur near the region where the tunnel oxide and field oxide meet, known as the reoxidation beak. The formation of the beak occurs during field oxide growth with additional growth of the beak occurring during the subsequent tunnel oxide growth in prior art processes. The presence of the beak causes the tunnel oxide in the source and drain regions to be thicker than in regions removed from the beak. This thickening near the source region can cause alterations to the erase characteristics of the cell. If the tunnel oxide is too thick, tunneling from the floating gate to source during erase is impeded and the erase times are thereby increased.
In addition to affecting erase characteristics, the shape and thickness of the reoxidation beak has important consequences on device scaling. If the beak is too long, the source and drain regions must extend far enough beyond the beak to allow tunneling during erase and injection during programming, respectively. The channel drawn dimension must therefore have a long enough length to allow for the source and drain to extend beyond the beaks without shorting together. This extra channel length requirement limits the scaling down of drawn dimensions, thereby limiting device density.
What is needed is a process which forms short, well defined reoxidation beaks, thereby improving the erase characteristics and allowing for device scaling.